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Recent advancements in low power and low noise front-end amplifiers have made it possible to support high-speed data transmission within the deep roll-off regions of conventional wireline channels. Despite being primarily limited by inter-symbol-interference (ISI), these legacy channels also require power-consuming front-end amplifiers due to increased insertion-loss at high frequencies. Wireline-like broadband channels, such as proximity communication and human-body-communication (HBC), as well as multi-lane, densely-packed channels, are further constrained by their high loss and unique channel responses which cause the received signal to be noise-limited. To address these challenges, this paper proposes the use of a discrete-time integrating amplifier as a low power <1 pJ/b using 65nm CMOS up to 5-6 Gb/s) alternative to traditional continuous-time front-end amplifiers. Integrating amplifiers also reduce the effects of noise due to its inherent current integrating process. The paper provides a detailed mathematical analysis of gain of two conventional and three novel and improved integrating amplifiers, accurate input referred noise estimations, signal-to-noise ratio, and a comparison of the integrating amplifier’s performance with that of a low-noise amplifier. The analysis identifies the most optimum integrator architecture and provides comparison with simulated results. This paper also develops theoretical expressions and provides in-depth understanding of input referred noise, while supporting them by simulations using 65nm CMOS technology node. Finally, a comparative analysis between low-noise amplifier and discrete-time integrating amplifier is presented to demonstrate power and noise benefits for both legacy and wireline-like channels, while providing an easier design space as integrator provides two-dimensional controllability for gain.